Silicon, foundries, GPUs — the substrate of everything.
AMD and Cerebras collaborate to integrate EPYC processors with Cerebras' wafer-scale AI engines in the Helios platform, targeting low-latency, high-throughput AI inference workloads for data centers.
Nvidia reveals architectural enhancements in its Rubin GPU platform focused on boosting inference performance and power efficiency across the data center hierarchy.
The ZEISS Crossbeam 750 FIBSEM introduces uninterrupted low-kV focused ion beam milling, enhancing TEM lamella preparation and tomography with higher resolution and faster acquisition.
AMD’s upcoming 10-core Medusa Point mobile APU achieves its highest Geekbench single-core score yet, surpassing all other x86 mobile chips and signaling a major leap in mobile CPU performance.
Nvidia's next-gen RTX 50 Super GPUs face launch delays as the cost of 3GB GDDR7 memory modules triples that of 2GB variants, threatening to push prices well beyond targets.
ASML’s decision to raise prices on its Low-NA EUV lithography tools challenges TSMC’s capital expenditure strategy, potentially reshaping foundry capacity growth and semiconductor node progression.
TSMC reports that its A14 process technology is progressing ahead of N2, delivering notable yield and performance gains, drawing strong interest from AI, HPC, and smartphone sectors.
Intel has become the first to deploy ASML’s High Numerical Aperture EUV lithography in high-volume production for select layers of its 18A Panther Lake processors, marking a key step in advanced node manufacturing.
Intel's $5.7 billion investment in a new fab in Ireland leverages its proven Fab 34 pipeline and Intel 3 node to address growing HPC market needs, marking a strategic pivot from its cancelled German and Polish projects.
Intel's new Starfire system-on-chip integrates an 18A CPU and advanced GPU on Intel 3 node, targeting space applications for US government use.
Apple is designing the M7 Ultra chip to support up to 1.5TB of unified memory and AI performance rivaling Nvidia's Blackwell accelerators, signaling a major leap in SoC capabilities contingent on easing memory constraints.
Colibrì’s proof-of-concept demonstrates a breakthrough in running a 1.5-TB AI model on minimal hardware, requiring only 25GB RAM and modest CPUs, promising accessible local AI deployments.
Japanese chipmaker Rapidus aims to disrupt the advanced foundry market with 2nm-class silicon priced around $20,000 per wafer, undercutting TSMC's rates and challenging established pricing norms.
As AI workloads demand ever-larger memory capacity and bandwidth, chipmakers explore lateral stacking of DRAM dies to overcome thermal limits and boost high-bandwidth memory density.
Intel's upcoming Nova Lake desktop processors will restore AVX-512 support, extending native 512-bit SIMD execution to both performance and efficiency cores, reversing the previous AVX-512 disablement and impacting AI, HPC, and multimedia workloads.
Intel's new XBM patent introduces a backend-transistor DRAM stack linked via UCIe chiplet interfaces, eliminating costly silicon interposers and integrating repair logic to address AI memory bottlenecks with reduced packaging complexity and cost.
Huawei plans to challenge Nvidia in South Korea by deploying Atlas SuperPods with 8,192 Ascend 950 AI accelerators, promising triple inference performance at a quarter of the cost.
South Korea’s top memory manufacturers are investing over $550 billion to build new DRAM and NAND fabs, aiming to alleviate global supply constraints and support AI-driven computing growth.
Intel has reportedly fixed critical wafer-to-wafer yield problems on its 18A node, enabling production ramp to 15,000 wafers monthly across two sites, a key step for its next-gen process viability.
Valar Atomics successfully powered an Nvidia RTX Spark desktop PC using its Ward 250 nuclear microreactor, marking a first in live nuclear microreactor demonstration. The startup plans a 30MW closed-loop AI data center with Nvidia, eliminating local water use.
AMD’s Linux kernel patch reveals integration of low-power cores in upcoming Zen 6 CPUs, adopting a hybrid architecture akin to Intel’s Alder Lake, targeting improved energy efficiency for background tasks.
Imec projects 0.3nm process nodes by 2038 and viable CFET transistors at 0.7nm, shifting focus from CPP scaling to cell size for transistor density gains.
Intel's upcoming 52-core Nova Lake processor ramps power consumption to 474W PL2, pushing motherboard design with triple 8-pin EPS connectors on the new LGA1954 platform.
Hybrid bonding in 3D chip stacking is breaking records, enabling denser, more efficient semiconductor integration as transistor scaling nears atomic limits.
IBM's breakthrough 0.7nm-class node leverages nanostack transistor architecture, doubling FEOL steps to achieve up to 50% performance uplift and 70% energy efficiency improvement over its 2nm-class technology.
OpenAI and Broadcom have introduced Jalapeño, a custom-designed inference ASIC, signaling a strategic shift towards purpose-built silicon for AI workloads. This collaboration highlights a rapid nine-month development cycle and emphasizes performance-per-watt optimization.
A tightening customs freeze on smuggled AI hardware has sent the black market price of five-year-old Nvidia A100 servers soaring to $82,000, underscoring the extreme premium on CUDA compatibility.
Qualcomm is diversifying its silicon portfolio with two new platforms targeting AI-driven wearables, signaling a shift toward ultra-low-power edge computing.
By replacing power-hungry floating-point multipliers with logarithmic addition, silicon startup Tensordyne aims to challenge Nvidia's dominance in hardware efficiency.
A collaboration between imec, ASML, and TSMC has successfully integrated n-type and p-type 2D-material transistors at a 50nm pitch on 300mm wafers, marking a major milestone for post-silicon sub-1nm scaling.
A presidential assertion about an Apple-Intel chip collaboration, though unconfirmed, highlights potential shifts in US semiconductor manufacturing and supply chain strategies.
Intel's enhanced 18A-P process has entered risk production, marking a significant step in its foundry roadmap by offering a 9% performance uplift at iso-power and 40% thermal resistance reduction. This 'drop-in' upgrade provides a compelling option for future silicon designs.
A physical teardown of Huawei's Kirin 9030 SoC reveals that SMIC's third-generation 7nm process achieves a 32.5nm metal pitch, but lacks the architectural scaling of Western nodes.
Intel is reportedly planning a second refresh of its Raptor Lake architecture under the Core 200 branding, leveraging mature silicon to fill budget tiers alongside next-generation Nova Lake processors.
AMD is targeting local AI development with a $3,999 Strix Halo-powered system, leveraging 128GB of unified memory to challenge Nvidia's workstation dominance.
With high-end GPU shipments to China blocked by US export controls, Nvidia is offering its Arm-based Vera server processors to Chinese data centers to maintain platform lock-in.
A pending U.S. International Trade Commission ruling could block imports of specific TSMC-manufactured chips, stemming from a patent infringement claim by rival UMC. This development, backed by U.S. lawmakers, raises significant concerns for global semiconductor supply chains and
A Dutch startup's reliance on GlobalFoundries' Dresden fab for its 'all-European' silicon highlights the geopolitical and corporate compromises of regional semiconductor sovereignty.
TSMC's extensive fab expansion, encompassing multi-fab N2 ramps and significant CoWoS/SoIC capacity growth, directly addresses critical bottlenecks to meet escalating demand for advanced AI accelerators.
A Chinese startup reports successful 8-inch photonic chip wafer production using nanoimprint lithography, potentially bypassing DUV restrictions and drastically cutting manufacturing costs by 90%.