Silicon, foundries, GPUs — the substrate of everything.
105 stories · page 3 of 5
As vertical high-bandwidth memory stacks hit a critical thermal ceiling, packaging engineers are turning to lateral integration and hybrid bonding to sustain AI accelerator scaling.
As traditional copper interconnects hit physical limits, major foundries are racing to deploy co-packaged optics, each taking a fundamentally different approach to silicon photonics integration.
As physical limits choke copper's conductivity at advanced nodes, researchers are turning to topological materials and exotic quasiparticles to solve the semiconductor interconnect crisis.
A technical deep dive into Nvidia's upcoming Vera CPU reveals a highly customized Arm architecture designed to eliminate memory and interconnect bottlenecks in massive AI clusters.
The semiconductor industry faces a prolonged memory supply crisis as the production of high-bandwidth memory for AI hardware consumes disproportionate wafer allocations.
Intel’s discontinuation of Optane memory, known for ultra-low latency and high endurance, leaves AI and memory-intensive workloads reliant on traditional DRAM amid ongoing supply constraints.
A prototype Microsoft Surface Laptop Ultra equipped with Nvidia's new N1X chip, dubbed RTX Spark, reveals promising performance improvements despite evident prototype limitations.
Researchers at Cornell Tech have developed an optical communication system enabling robots to receive AI model updates on the fly, using LED-to-lens data transmission.
AMD and Cerebras collaborate to integrate EPYC processors with Cerebras' wafer-scale AI engines in the Helios platform, targeting low-latency, high-throughput AI inference workloads for data centers.
Nvidia reveals architectural enhancements in its Rubin GPU platform focused on boosting inference performance and power efficiency across the data center hierarchy.
The ZEISS Crossbeam 750 FIBSEM introduces uninterrupted low-kV focused ion beam milling, enhancing TEM lamella preparation and tomography with higher resolution and faster acquisition.
AMD’s upcoming 10-core Medusa Point mobile APU achieves its highest Geekbench single-core score yet, surpassing all other x86 mobile chips and signaling a major leap in mobile CPU performance.
Nvidia's next-gen RTX 50 Super GPUs face launch delays as the cost of 3GB GDDR7 memory modules triples that of 2GB variants, threatening to push prices well beyond targets.
ASML’s decision to raise prices on its Low-NA EUV lithography tools challenges TSMC’s capital expenditure strategy, potentially reshaping foundry capacity growth and semiconductor node progression.
TSMC reports that its A14 process technology is progressing ahead of N2, delivering notable yield and performance gains, drawing strong interest from AI, HPC, and smartphone sectors.
Intel has become the first to deploy ASML’s High Numerical Aperture EUV lithography in high-volume production for select layers of its 18A Panther Lake processors, marking a key step in advanced node manufacturing.
Intel's $5.7 billion investment in a new fab in Ireland leverages its proven Fab 34 pipeline and Intel 3 node to address growing HPC market needs, marking a strategic pivot from its cancelled German and Polish projects.
Intel's new Starfire system-on-chip integrates an 18A CPU and advanced GPU on Intel 3 node, targeting space applications for US government use.
Apple is designing the M7 Ultra chip to support up to 1.5TB of unified memory and AI performance rivaling Nvidia's Blackwell accelerators, signaling a major leap in SoC capabilities contingent on easing memory constraints.
Colibrì’s proof-of-concept demonstrates a breakthrough in running a 1.5-TB AI model on minimal hardware, requiring only 25GB RAM and modest CPUs, promising accessible local AI deployments.
Japanese chipmaker Rapidus aims to disrupt the advanced foundry market with 2nm-class silicon priced around $20,000 per wafer, undercutting TSMC's rates and challenging established pricing norms.
As AI workloads demand ever-larger memory capacity and bandwidth, chipmakers explore lateral stacking of DRAM dies to overcome thermal limits and boost high-bandwidth memory density.
Intel's upcoming Nova Lake desktop processors will restore AVX-512 support, extending native 512-bit SIMD execution to both performance and efficiency cores, reversing the previous AVX-512 disablement and impacting AI, HPC, and multimedia workloads.
Intel's new XBM patent introduces a backend-transistor DRAM stack linked via UCIe chiplet interfaces, eliminating costly silicon interposers and integrating repair logic to address AI memory bottlenecks with reduced packaging complexity and cost.