Imec, ASML, and TSMC Demonstrate 300mm Integration of Complementary 2D Transistors

The physical limits of bulk silicon have long loomed over the semiconductor industry, forcing researchers to look beyond traditional channels for sub-1nm nodes. In a significant step toward commercializing post-silicon electronics, a joint effort by research hub imec, lithography leader ASML, and foundry giant TSMC has demonstrated the co-integration of n-type and p-type transistors using atomically thin two-dimensional (2D) materials. Fabricated on a standard 300mm pilot line, the complementary transistors achieved a tight 50nm contact pitch, proving that these novel materials can be processed using industry-standard manufacturing equipment.

The breakthrough relies on transition metal dichalcogenides (TMDs), a class of semiconductor materials that can be scaled down to monolayer thicknesses—often just three atoms thick—without suffering from the severe short-channel effects that plague silicon at ultra-scaled dimensions. Historically, the industry has struggled to integrate both n-type (electron-conducting) and p-type (hole-conducting) 2D transistors on the same substrate due to differing growth temperatures, contact resistance issues, and material compatibility. By successfully fabbing both polarities on a single wafer, the partners have cleared a fundamental hurdle for complementary metal-oxide-semiconductor (CMOS) logic architectures of the future.

Achieving this at a 50nm pitch on 300mm silicon wafers is highly significant for foundry economics. It transitions 2D materials from isolated university laboratory experiments to scalable, high-volume manufacturing (HVM) pathways. ASML’s advanced lithography systems and TSMC’s manufacturing expertise were critical in addressing the overlay tolerances and defectivity challenges inherent in transferring and patterning monolayer films. The use of a 300mm pilot line ensures that the deposition, etching, and planarization steps developed for these TMDs are compatible with existing fab infrastructures, minimizing the capital expenditure required for eventual deployment.

While this milestone validates the feasibility of 2D CMOS, commercial implementation remains years away. Engineers must still optimize contact resistance, improve gate dielectric interfaces to reduce trap states, and scale up the synthesis of defect-free TMD monolayers over entire 300mm wafers. However, as gate-all-around (GAA) nanosheets approach their physical scaling limits in the coming years, complementary 2D-channel transistors represent the primary candidate to succeed them, offering a viable roadmap for dimensional scaling well into the angstrom era.