All stories tagged lithography on The Silicon Valley News.
Researchers in China have demonstrated 3nm-class gate-all-around transistors without EUV lithography, signaling a shift in manufacturing strategy despite significant yield and density hurdles.
TSMC has detailed its timeline for integrating High-NA EUV lithography into its production roadmap by 2030, targeting A10 or A11 process technologies, marking a critical step for future transistor scaling and chip density.
Intel has processed over one million wafers using High-NA EUV lithography, positioning itself ahead of industry competitors in critical next-generation manufacturing technology, complemented by advancements in 6x12 photomasks.
LG's new maskless Laser Direct Imaging machine aims to solve the critical throughput constraints currently plaguing high-density chip packaging and interconnect scaling.
ASML’s decision to raise prices on its Low-NA EUV lithography tools challenges TSMC’s capital expenditure strategy, potentially reshaping foundry capacity growth and semiconductor node progression.
Intel has become the first to deploy ASML’s High Numerical Aperture EUV lithography in high-volume production for select layers of its 18A Panther Lake processors, marking a key step in advanced node manufacturing.